The invention relates to a semiconductor device having a semiconductor element of the MIS type comprising a monocrystalline semiconductor body, one surface of which is provided with a comparatively thin dielectric layer which constitutes the gate dielectric of the MIS element and on which a gate electrode of doped semiconductor material is provided for influencing the surface potential in the semiconductor body.
Semiconductor elements of the MIS type are to be understood to mean not only insulated gate field effect transistors, charge transfer devices (CCD's and BBD's), and other devices in which a charge transport can be controlled in the semiconductor body by means of the gate electrode, but also devices in which the gate electrode constitutes a field plate, more particularly for influencing breakdown voltages.
In semiconductor technology, polycrystalline silicon is used very frequently as a gate electrode. The popularity of polycrystalline silicon, designated as polysilicon or poly, is due to a large extent to the fact that polysilicon is a particularly suitable material in self-registering MOS processes, in which the gate electrode and the source/drain zones are defined by the same masking step. In integrated circuits, polysilicon is used not only as a gate electrode, but also for the wiring.
In order inter alia to keep dissipation and/or RC-times at a minimum, it is common practice to make the resistance of the polysilicon generally as small as possible, for example, by doping the poly to the highest possible extent (10.sup.20 -10.sup.22 atoms/cm.sup.3) or by converting the poly with the aid of a suitable metal into a silicide.
The gate dielectric is constituted in most cases by silicon oxide, which when the semiconductor body itself consists of silicon, can be obtained by oxidation of the surface of the semiconductor body. When the gate electrode constitutes a gate electrode of a field effect device (transistor or, for example, CCD), an oxide layer having a thickness of the order of 0.1 .mu.m is generally used. In those cases in which the device has to be operated at higher voltages or in which the gate electrode constitutes a field plate for increasing breakdown voltages, the thickness of the gate dielectric may be larger.
In the choice of the thickness of the gate dielectric, several factors may play a part, which may lead to different requirements with respect to the thickness. The ultimate choice will often be a compromise, in which the various requirements are satisfied to a larger or lesser extent (or are not satisfied at all) depending upon their importance. Consequently, the operation of the device is often basically satisfactory, but further improvements would be desirable. This will be explained more fully with reference to several examples.
As is known, A CCD is a device in which a series of discrete charge packets are transported under the influence of clock signals through a channel located at or near the surface of the semiconductor body. The clock signals are supplied to a number of clock electrodes which are arranged as a row on an oxide layer covering the surface and each constitutes an MIS capacitor with the semiconductor body. At a given amplitude of the clock signals, the maximum size of the charge packets is determined by the value of the MIS capacitances. In general, the requirements imposed on the maximum charge packets in connection, for example, with the dynamic power or the signal-to-noise ratio make a maximum capacitance per unit surface area desirable. According to the prior art, this preference is more important, as with the aid of photolithographic techniques the lateral dimensions of the device or at least the various components thereof can be made smaller.
In order to obtain a high charge storage capacity per unit surface area, it is desirable to make the oxide thickness as small as possible or at least as small as is justified in connection with a still reasonable manufacturing output yield.
In order to transfer charge rapidly from one place to another, decoupling between the charge and the electrode of the first charge storage site is desirable. Due to such a decoupling, the formation of drift fields (fringing fields) in the channel is possible, as a result of which the transfer process is improved (more rapidly and/or with lower loss). In this connection, it would be advantageous to make the oxide thickness as large as possible. In the manufacture of a CCD, no attention is paid to this aspect, but the oxide thickness is chosen to be as small as possible in order to obtain a maximum capacity.
It may also be desirable that thin and thick oxide are both simultaneously available. As is known, for example, in a D-MOST or a DSA-MOST, the source and drain zones are separated from each other by a channel region and an adjoining drift region. In a frequently used method of manufacturing D-MOST's, first the-thin-gate dielectric is applied; then the gate electrode is formed and subsequently the zone forming the channel region and the source and drain zones are provided while the gate electrode forms part of the doping mask. In a transistor thus manufactured, the drift region is separated from the gate electrode by the thin gate oxide. However, in connection with the high-frequency properties of the transistor, a decoupling between the gate region and the drift region is desirable. Such a decoupling could be obtained by means of thick oxide above the drift region. However, the process of accurately applying the thin oxide above the channel region and the thick oxide above the drift region requires very critical alignment steps, which become more difficult as the dimensions become smaller. For this reason, generally, the thin gate oxide is also applied above the drift region.
The overlapping capacitance of the gate electrode with other parts of the transistors can play a part in various types of transistors, which are intended for various application. For example, for tuning circuits, an MOS transistor may be required, which, in order that it can be utilized as a switch in this type of circuit, has a low "on"-resistance and, in the "off" state, a low capacitance. When for the sake of simplicity it is assumed that a conventional D-MOST is used of the kind described above, a low on resistance can be obtained by carrying out an additional implantation in the drift region of the transistor, as a result of which at the relevant area the doping is increased. Due to this implantation, the oxide thickness remaining unchanged, the drain/gate capacitance and hence also the drain/source capacitance would increase. In order to render such a transistor suitable for use in tuning circuits, a decoupling between channel/drain and the gate electrode would therefore be desirable.
It may be advantageous not only in connection with undesirable parasitic capacitances, but also in other respects to electrically decouple the gate electrode and the semiconductor body.
As is known, in high-voltage transistors, the breakdown voltage may be increased by means of so-called field plates, as a result of which the electrical field strength at the surface is decreased. In the non-prepublished Dutch Patent Application No. 8200464, corresponding to U.S. Ser. No. 352,450, now abandoned, the contents of which are incorporated by reference in the present application, the use of field plates in combination with the resurf principle is described. The resurf principle is known per se, for example, from the article by J. A. Appels et al entitled "Thin Layer High-Voltage Devices (Resurf Devices)" In Philips Journal of Research, Vol. 35, No. 1, 1980, pg 1-3. Such devices comprise a substrate region of the one, for example, the p-, conductivity type and an adjoining n-type surface layer, for example, an epi layer, in which a circuit element is formed and which forms a pn junction with the substrate: In these known devices, the breakdown voltage may be very high and may closely approach and even equal the so-called unidimensional calculated value (at which the pn junction is assumed to be planar and to extend infinitely) due to the fact that a high reverse voltage across the substrate/epi pn junction the field strength at the surface is considerably decreased by the complete depletion of the semiconductor layer.
A disadvantage of known resurf devices is that the overall doping of the surface layer is approximately 10.sup.12 atoms/cm.sup.2. This results in that in the known resurf devices, the current-conveying power of the semi-conductor layer is lower than is sometimes desirable. In order to be able to choose a higher Nd product while maintaining the breakdown properties, in the above-mentioned Dutch Application No. 8200464 it has been proposed to provide on the surface a field electrode or field plate, as a result of which depletion of the surface layer can take place not only from the substrate, as in the known device, but also from the surface. In FIGS. 1 and 2 of the prior Application, D-MOST's are shown of the resurf type, in which the said field plate is connected to the insulated gate and to the source electrode, respectively.
If these field plates were to extend throughout the drift region as far as above the contact zone of the drain, it is possible for the maximum permissible voltage to be reduced again to far below the said calculated value of the breakdown voltage of the pn junction between the substrate and the surface layer. This may be due to the large voltage difference over the comparatively thin oxide between the drain and the field plate located immediately above the latter, as a result of which breakdown can occur over the oxide and/or breakdown is produced in the silicon. A possible method of preventing such a breakdown could be for the field plate not to be provided as far as above the drain zone, and so only above a part of the drift region. Such a method has the disadvantage, however, that the surface potential cannot be controlled by the field plate in the whole drift region. Another method of preventing breakdown, which consists in forming thick oxide at least locally above the drift region, may give rise to step coverage problems and is therefore less suitable. The problems just mentioned with respect to field plates apply not only to resurf elements, but in general to devices, in which a field plate is located above a surface region in the semiconductor body, which exhibits a large voltage difference with respect to the field plate.